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Si4313-B1
Table 16. Register Descriptions (Continued)
Add
R/W
Function/Desc
Data
POR
D7
D6
D5
D4
D3
D2
D1
D0
Default
2A
2B
2C
2D
2E
R/W
R
R/W
R/W
R/W
AFC Limiter
AFC Correction Read
OOK Counter Value 1
OOK Counter Value 2
Slicer Peak Hold
Afclim[7]
afc_corr[9]
afc_corr[9]
ookcnt[7]
Reserved
Afclim[6]
afc_corr[8]
afc_corr[9]
ookcnt[6]
attack[2]
Afclim[5]
afc_corr[7]
ookfrzen
ookcnt[5]
attack[1]
Afclim[4]
afc_corr[6]
peakdeten
ookcnt[4]
attack[0]
Afclim[3]
afc_corr[5]
madeten
ookcnt[3]
decay[3]
Afclim[2]
afc_corr[4]
ookcnt[10]
ookcnt[2]
decay[2]
Afclim[1]
afc_corr[3]
ookcnt[9]
ookcnt[1]
decay[1]
Afclim[0]
afc_corr[2]
ookcnt[8]
ookcnt[0]
decay[0]
00h
00h
18h
BCh
26h
2F
Reserved
30
R/W
FIFO Configuration
fiforx
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8Dh
31-34
Reserved
35
36
37
38
39
R/W
R/W
R/W
R/W
R/W
Preamble Detection Control
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
preath[4]
sync[31]
sync[23]
sync[15]
sync[7]
preath[3]
sync[30]
sync[22]
sync[14]
sync[6]
preath[2]
sync[29]
sync[21]
sync[13]
sync[5]
preath[1]
sync[28]
sync[20]
sync[12]
sync[4]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
rssi_off[2]
sync[26]
sync[18]
sync[10]
sync[2]
rssi_off[1]
sync[25]
sync[17]
sync[9]
sync[1]
rssi_off[0]
sync[24]
sync[16]
sync[8]
sync[0]
2Ah
2Dh
D4h
00h
00h
3A-4E
Reserved
4F
R/W
ADC8 Control
Reserved
Reserved
adc8[5]
adc8[4]
adc8[3]
adc8[2]
adc8[1]
adc8[0]
10h
50-5F
Reserved
60
R/W
Channel Filter Coefficient
Inv_pre_th[3]
Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0]
chfiladd[3]
chfiladd[2]
chfiladd[1]
chfiladd[0]
00h
Address
61
Reserved
62
R/W
Crystal Oscillator/Control Test
pwst[2]
pwst[1]
pwst[0]
clkhyst
enbias2x
enamp2x
bufovr
enbuf
24h
63-68
Reserved
69
R/W
AGC Override 1
Reserved
sgi
agcen
lnagain
pga3
pga2
pga1
pga0
20h
6A-6C
Reserved
70
71
73
74
75
76
77
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Modulation Mode Control 1
Modulation Mode Control 2
Frequency Offset 1
Frequency Offset 2
Frequency Band Select
Nominal Carrier Frequency 1
Nominal Carrier Frequency 0
Reserved
rxclk[1]
fo[7]
Reserved
Reserved
fc[15]
fc[7]
Reserved
rxclk[0]
fo[6]
Reserved
sbsel
fc[14]
fc[6]
Reserved
dtmod[1]
fo[5]
Reserved
hbsel
fc[13]
fc[5]
Reserved
dtmod[0]
fo[4]
Reserved
fb[4]
fc[12]
fc[4]
manppol
eninv
fo[3]
Reserved
fb[3]
fc[11]
fc[3]
enmaninv
fd[8]
fo[2]
Reserved
fb[2]
fc[10]
fc[2]
enmanch
modtyp[1]
fo[1]
fo[9]
fb[1]
fc[9]
fc[1]
Reserved
modtyp[0]
fo[0]
fo[8]
fb[0]
fc[8]
fc[0]
0Ch
00h
00h
00h
75h
BBh
80h
78
Reserved
79
R/W
Frequency Hopping Channel
fhch[7]
fhch[6]
fhch[5]
fhch[4]
fhch[3]
fhch[2]
fhch[1]
fhch[0]
00h
Select
7A
R/W
Frequency Hopping Step Size
fhs[7]
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
fhs[0]
00h
7B
Reserved
7E
7F
R/W
R/W
RX FIFO Control
FIFO Access
Reserved
fifod[7]
Reserved
fifod[6]
rxafthr[5]
fifod[5]
rxafthr[4]
fifod[4]
rxafthr[3]
fifod[3]
rxafthr[2]
fifod[2]
rxafthr[1]
fifod[1]
rxafthr[0]
fifod[0]
37h
—
Note: Detailed register descriptions are available in “AN589: Si4313 Detailed Register Descriptions.”
42
Rev. 1.0
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